Universal Asynchronous Receiver Transmitter

A universal asynchronous receiver–transmitter (UART) is an electronic subsystem used for asynchronous serial communication between digital devices. It converts parallel data from a computer or microcontroller into serial form for transmission and reassembles serial data back into parallel form upon reception. Because timing in asynchronous communication is controlled by start and stop bits rather than a shared clock, UARTs remain widely used for simple, low-cost, and low-pin-count communication links in embedded systems and computer peripherals.
UARTs handle only the digital framing and timing of data, while electrical signalling standards such as RS-232, RS-485, or TTL-level serial are managed by external driver circuits. Historically, current-loop signalling was also used in early teletypewriter systems.

Overview and Function

A UART manages the transmission of information one bit at a time, beginning with a start bit, followed by a selectable number of data bits, an optional parity bit, and one or more stop bits. Bytes are sent least significant bit first, a convention inherited from early teleprinter systems. Because the protocol embeds control information within the data stream itself, timing remains synchronised without the need for a dedicated clock line.
A related device, the universal synchronous and asynchronous receiver–transmitter (USART), extends functionality to synchronous operation by incorporating clocked data transfer mechanisms. Within the OSI model, UART operation is generally associated with Layer 2, the data link layer.
UARTs are typically implemented as integrated circuits and are commonly embedded within microcontrollers. Special-purpose variants are also used for low-speed automotive networks such as LIN, and in secure interfaces for smart cards and SIM cards.

Historical Development

The origins of the UART lie in early telegraphic communication. Early schemes employed variable-length pulses, as in Morse code, or mechanical commutators producing fixed-length pulses to encode characters. As teleprinters became standard input/output devices for small computers, fixed character formats using 5, 6, 7, or 8 data bits became widespread.
One of the earliest electronic UARTs was developed by Gordon Bell at Digital Equipment Corporation (DEC) for the PDP-1 computer. This first design occupied an entire circuit board, known as a line unit. Bell’s principal innovation was the use of digital sampling of the incoming signal, replacing earlier analogue timing circuitry that depended on manually adjusted components. DEC later condensed the design into one of the earliest single-chip UARTs.
The first widely available commercial single-chip UART, the Western Digital WD1402A, appeared around 1971 and became an influential integrated circuit. Other notable early devices included the Signetics SCN2651 and the National Semiconductor 8250, the latter becoming standard in IBM PC serial adapter cards.
By the 1990s, UARTs evolved to include on-chip FIFO buffers, enabling higher transmission speeds without the risk of data loss and with reduced processor overhead. The National Semiconductor 16550 introduced a 16-byte FIFO and inspired several improved derivatives, including the 16C550, 16C650, 16C750, and 16C850.
Manufacturers often used different terminology for similar devices. Intel referred to its 8251 device as a Programmable Communication Interface, reflecting its ability to operate synchronously. MOS Technology marketed its 6551 as an Asynchronous Communications Interface Adapter (ACIA), while Motorola used the term Serial Communications Interface (SCI) from the mid-1970s for its asynchronous serial interface modules. Zilog produced a range of Serial Communication Controllers (SCCs), supporting multi-protocol serial links.
From the early 2000s onwards, IBM-compatible personal computers phased out external RS-232 COM ports in favour of USB. This change led to widespread adoption of USB-to-serial adapters, often built around chips from FTDI or Cypress Semiconductor. Nevertheless, most processors still incorporate internal UART modules, offering designers a straightforward interface for legacy serial protocols.

Architecture and Components

A UART typically contains several essential subsystems:

• Clock generator, operating at a multiple of the bit rate to allow sampling at the midpoint of each bit period.
• Shift registers, used to convert between parallel data internally and serial data on the transmission line.
• Transmit and receive buffers, often implemented as FIFOs to support burst transfers.
• Control logic, managing read/write operations and signal framing during transmission and reception.

UARTs do not normally generate external signal levels directly. Dedicated interface devices convert logic-level signals to the appropriate electrical standard—such as ±12 V signalling for RS-232 or differential signalling for RS-485.
Serial communication may operate in three modes:

• Simplex, permitting transmission in only one direction.
• Half-duplex, in which devices take turns sending and receiving.
• Full-duplex, where bidirectional communication occurs simultaneously.

For reliable operation, both communicating UARTs must use the same configuration, including data bit length, stop bit length, parity scheme, and voltage level. When different voltage standards are used—such as 3.3 V and 5 V logic—a level-shifting circuit is required.

Data Framing and Protocol Characteristics

A UART data frame comprises a fixed sequence of signalling elements:

• Idle state: logic high, maintained between characters.
• Start bit: logic low, indicating that data transmission is commencing.
• Data bits: typically 5–9 bits representing the character.
• Parity bit (optional): used for rudimentary error detection, with even or odd parity options.
• Stop bits: one or two logic-high intervals marking the end of the character.

The transition from a low start bit to a high stop bit ensures at least two signal changes between characters. If the line remains low for longer than a character time, the receiver detects a break condition.
In the common configuration 8N1—eight data bits, no parity, one stop bit—protocol efficiency is 80 %, because 8 of the 10 transmitted bits represent payload data. In contrast, Ethernet can achieve higher throughput with large frames but suffers reduced efficiency when transmitting very small payloads due to fixed overhead.
Legacy telegraph conventions are retained in the idle high state, historically used to indicate that the line was powered and unbroken.

Receiver Operation

A UART receiver is controlled by an internal clock running at a multiple—commonly eight or sixteen times—of the bit rate. It monitors the incoming signal at each clock cycle to detect a possible start bit. If the low level persists for at least half a bit period, the receiver interprets it as a valid start bit. Thereafter, the receiver samples the line at predetermined intervals to reconstruct the remaining data, parity, and stop bits. Once a complete frame has been assembled, the UART outputs the corresponding byte to the parallel interface.