India’s Semiconductor Policies and Schemes

Overview

India’s semiconductor policy framework is aimed at building a domestic chip manufacturing ecosystem, reducing dependence on imports, and strengthening the country’s role in global electronics supply chains. The support structure combines fiscal incentives, design support, packaging assistance, and state-level facilitation to cover the chip value chain from design to assembly.

The centrepiece of this framework is the India Semiconductor Mission, which functions as an independent specialised division under the Ministry of Electronics and Information Technology (MeitY). It anchors the government’s long-term push for semiconductor self-reliance.

India Semiconductor Mission and programme evolution

• Institutional base: The India Semiconductor Mission serves as the administrative and implementation arm for semiconductor policy support.
• Purpose: It is designed to build a complete semiconductor ecosystem, including fabrication, assembly, testing, packaging, design, and supply-chain capabilities.
• Strategy: The mission seeks to attract investment, reduce import reliance, and create a manufacturing base that can serve domestic and export markets.

Semicon India Programme 1.0

• Launch: December 2021.
• Initial outlay: ₹76,000 crore.
• Coverage: Financial support for silicon fabs, display fabs, and compound semiconductors.
• Support structure: Offered up to 50% of capital expenditure support on a pari-passu basis for approved manufacturing and packaging units.
• Implementation impact: Helped in the approval of multiple semiconductor plants across states such as Gujarat, Odisha, and Assam.
• Facility types: Included outsourced assembly, testing, marking, and packaging (ATMP) units.

Semicon India Programme 2.0

• Approval: Cleared by the Union Cabinet.
• Expanded outlay: ₹1,27,500 crore.
• Objective: To deepen technological capabilities and broaden the domestic semiconductor base.
• Focus areas: Domestic semiconductor intellectual property, specialised equipment production, raw material supply chains, and advanced packaging technologies.
• Capital support: Provides 40% capital expenditure backing for complementary metal-oxide-semiconductor (CMOS) silicon fabs.
• Additional support: Offers 35% support for compound semiconductor and advanced packaging units.

Core incentive schemes and support pillars

• Design Linked Incentive Scheme: Supports domestic startups and micro, small and medium enterprises (MSMEs) through seed capital, risk assistance, and deployment-linked incentives.
• Design ecosystem: Helps offset the high cost of electronic design automation tools and chip tape-outs.
• Fabless development: Aims to nurture a stronger domestic fabless semiconductor ecosystem.
• Packaging and testing support: Encourages establishment of outsourced assembly, testing, marking and packaging units.
• Capacity gap: Intended to bridge domestic shortages in semiconductor back-end infrastructure.
• Advanced packaging: Promotes heterogeneous integration and three-dimensional packaging facilities.
• Technology relevance: These advanced facilities are important for high-performance computing, artificial intelligence, and telecommunication hardware.

Policy structure across the semiconductor value chain

Role of states, industry, and academia

• State incentives: State governments complement central support through regional semiconductor policies.
• Land support: These policies often include land subsidies for manufacturing projects.
• Cost relief: Power tariff concessions and stamp duty exemptions are also used to attract investment.
• Manufacturing locations: The first commercial semiconductor assembly and test facility under the mission began operations in Sanand, Gujarat.
• Skill development: Academic partnerships with technical institutions are used to train specialised manpower.
• Workforce focus: Training is aimed at cleanroom engineers and VLSI design professionals.

Why the policy framework matters for India

• Import reduction: A domestic chip ecosystem can reduce dependence on imported semiconductors.
• Supply-chain resilience: Local capacity improves resilience against global disruptions.
• Investment attraction: Incentives are intended to draw both domestic and international investors.
• Industrial depth: The policy covers design, fabrication, packaging, and equipment supply rather than only one segment.
• Technology upgrading: Advanced packaging and intellectual property support indicate a move beyond basic assembly.

Key Prelims Takeaways

• India Semiconductor Mission: Independent specialised division under MeitY.
• Semicon India 1.0: Launched in December 2021 with an outlay of ₹76,000 crore.
• Semicon India 2.0: Approved with an expanded outlay of ₹1,27,500 crore.
• Capital support: Up to 50% under Semicon 1.0; 40% for CMOS silicon fabs and 35% for compound semiconductor and advanced packaging units under Semicon 2.0.
• Design Linked Incentive: Supports startups and MSMEs in chip design and tape-out costs.
• Key facility type: Outsourced assembly, testing, marking and packaging (ATMP) is a major policy focus.
• First commercial facility: Began operations in Sanand, Gujarat.