Common Computer Architecture Concepts for Prelims: Bus, Registers, Cache Levels

Computer architecture encompasses the foundational hardware components and organizational structures that dictate how processors communicate, store, and execute data instructions.

System Bus Architecture

The system bus serves as the primary communication highway connecting the central processing unit, memory, and peripheral input-output devices.

Functional Bus Categories

• Data Bus: Transports actual data instructions between the processor, memory modules, and peripheral controllers, operating on a bidirectional architecture.
• Address Bus: Carries memory locations and physical storage addresses from the central processing unit to main memory, determining the maximum addressable memory capacity.
• Control Bus: Transmits command signals, read-write timing orders, and interrupt requests to synchronize operations across hardware components.

Processor Registers

Registers are ultra-fast, volatile storage locations housed directly inside the central processing unit for immediate data manipulation.

Essential Register Types

• Accumulator: Stores intermediate arithmetic and logical results generated during arithmetic logic unit operations.
• Program Counter: Holds the memory address of the next instruction scheduled for execution within the instruction cycle.
• Instruction Register: Stores the current instruction fetched from memory while it is being decoded and executed.
• Memory Address Register: Temporarily holds the physical memory address currently being accessed for read or write operations.
• Stack Pointer: Manages memory stack operations by tracking the address of the most recent item added to the execution stack.

Memory Hierarchy and Cache Levels

Cache memory acts as a high-speed volatile buffer positioned between the processor core and main system random-access memory to bridge speed differentials.

Cache Tier Classification

• Level 1 Cache: The fastest and smallest cache tier integrated directly onto the processor core, operating at central processing unit clock speeds with minimal latency.
• Level 2 Cache: A larger secondary memory buffer located close to the processor core, offering higher capacity with slightly increased access delays.
• Level 3 Cache: A shared memory tier distributed across multi-core processors, serving as a common pool for rapid data exchange between cores.

Comparative Overview of Architectural Components

• The von Neumann architecture utilizes a shared memory space for both program instructions and data, creating the classic bottleneck where data and instructions cannot be accessed simultaneously.
• The Harvard architecture separates data storage and instruction memory into distinct physical pathways, allowing simultaneous access and higher instruction throughput.
• Static Random-Access Memory forms the physical semiconductor technology used to construct high-speed processor cache tiers due to its flip-flop circuitry design.
• Dynamic Random-Access Memory requires constant electrical refreshing and serves as the primary material for standard system random-access memory modules.
• Memory mapping allows input-output device controllers to share the same address space as main memory, enabling unified read and write commands.