IIT Madras to Host Digital India RISC-V Symposium 2026

IIT Madras will host the 3rd Digital India RISC-V (DIR-V) Symposium 2026 on 1-2 August 2026 at the IIT Madras Research Park in Chennai, Tamil Nadu. The event is being organised with the Ministry of Electronics and Information Technology (MeitY), Government of India, and RISC-V International.

RISC-V Architecture

RISC-V is an open standard instruction set architecture used for processor design. It belongs to the Reduced Instruction Set Computer (RISC) family and allows custom processor development without dependence on a proprietary architecture.

Digital India DIR-V Initiative

The Digital India RISC-V symposium is linked to India’s work on indigenous processor technologies and hardware innovation. The 2026 theme is “Empowering Bharat’s Semiconductor Future”, and the event covers secure computing systems, artificial intelligence, and the RISC-V ecosystem in India.

Event Format and Participants

The symposium will bring together policymakers, global technology experts, researchers, startups, industry leaders, investors, faculty members, and students. A DIR-V Grand Challenge Hackathon will also be held for student and startup solutions using RISC-V technologies.

Important Facts for Exams

• RISC-V is an open-source instruction set architecture developed at the University of California, Berkeley.
• MeitY is the nodal ministry for electronics, information technology, and digital governance in India.
• IIT Madras Research Park is located in Chennai, Tamil Nadu.
• The last date to register for the symposium is 28 July 2026.

Semiconductor Ecosystem in India

India’s semiconductor policy framework includes chip design, electronics manufacturing, and secure digital infrastructure. The symposium is aligned with the Government of India’s objective of building a trusted hub for semiconductor design and related technologies.