Computer Architecture: Buses, Registers and Cache Levels

Computer architecture explains how a computer system organises its core hardware so that the processor can communicate with memory and input-output devices, and execute instructions efficiently. It covers the structure of buses, the role of registers, and the cache hierarchy that helps bridge the speed gap between the CPU and main memory.

System Bus Architecture

The system bus is the main communication pathway linking the central processing unit, memory, and peripheral input-output devices. It carries data, addresses, and control signals across hardware components so that operations can be coordinated properly.

• Data bus: Transfers actual data and instructions between the processor, memory modules, and peripheral controllers. It is generally bidirectional.
• Address bus: Carries memory locations and physical storage addresses from the CPU to main memory. It helps determine the maximum addressable memory capacity.
• Control bus: Transmits command signals, read-write timing orders, and interrupt requests to synchronize hardware operations.

Processor Registers

Registers are ultra-fast, volatile storage locations placed directly inside the CPU for immediate data handling. They store values needed at the start of instruction execution and are much faster than main memory.

• Accumulator: Stores intermediate arithmetic and logical results generated during arithmetic logic unit operations.
• Program Counter: Holds the memory address of the next instruction to be executed in the instruction cycle.
• Instruction Register: Stores the current instruction fetched from memory while it is being decoded and executed.
• Memory Address Register: Temporarily holds the physical memory address currently being accessed for read or write operations.
• Stack Pointer: Tracks the address of the most recent item added to the execution stack.

Exam fact: Registers are the fastest storage elements in the processor hierarchy and are used for immediate instruction processing.

Cache Memory and Its Levels

Cache memory is a high-speed volatile buffer placed between the processor core and main RAM. It reduces the time needed to access frequently used data and instructions.

• Level 1 cache: The fastest and smallest cache tier, integrated directly onto the processor core and operating at CPU clock speeds with minimal latency.
• Level 2 cache: A larger secondary buffer located close to the processor core, with higher capacity and slightly increased access delay.
• Level 3 cache: A shared cache tier used in multi-core processors, serving as a common pool for rapid data exchange between cores.

Memory Hierarchy and Architectural Models

Computer memory is organised in a hierarchy based on speed, cost, and capacity. Registers are the fastest, followed by cache memory, then main memory. This structure helps the processor access critical data quickly while keeping overall cost practical.

• Main memory: The volatile workspace for active programs, usually provided by external RAM modules.
• System bus: Slower than registers and cache, but essential for communication across the motherboard pathways.
• Registers and cache: Used for rapid storage close to the CPU, while main memory stores larger working data.

The von Neumann architecture uses a shared memory space for both program instructions and data. This creates the classic bottleneck because instructions and data cannot be accessed simultaneously from the same path. In contrast, the Harvard architecture separates instruction memory and data storage into distinct physical pathways, allowing simultaneous access and higher instruction throughput.

RAM, SRAM and DRAM

Different memory technologies are used for different layers of the memory system. Static Random-Access Memory (SRAM) is used to build high-speed cache because of its flip-flop circuitry design. Dynamic Random-Access Memory (DRAM) requires constant electrical refreshing and is used as the primary form of standard system RAM.

• SRAM: Faster and more suitable for cache memory.
• DRAM: Denser and used for main memory, but slower than SRAM.
• Volatility: Both cache and main memory are volatile and lose data when power is removed.

Memory Mapping and System Relevance

Memory mapping allows input-output device controllers to share the same address space as main memory. This makes it possible to use unified read and write commands for both memory and certain device operations. For prelims, the key idea is that buses carry communication, registers enable immediate processing, and cache reduces the CPU-memory speed gap.

Key Prelims Takeaways

• System bus: The main highway connecting CPU, memory, and input-output devices.
• Data bus: Transfers data and instructions; usually bidirectional.
• Address bus: Carries memory addresses and determines addressable memory capacity.
• Control bus: Sends control signals, timing orders, and interrupts.
• Registers: Fastest CPU storage used for immediate instruction processing.
• Program Counter: Holds the address of the next instruction.
• Cache hierarchy: L1 is fastest, L2 is larger, and L3 is shared in multi-core processors.
• SRAM vs DRAM: SRAM is used for cache; DRAM is used for main memory.